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ltc2489 1 2489f r source ( ) 1 +fs error (ppm) ?0 0 20 1k 100k 2489 ta01b ?0 ?0 ?0 10 100 10k 40 60 80 v cc = 5v v ref = 5v v in + = 3.75v v in = 1.25v f o = gnd t a = 25 c c in = 1 f 16-bit 2-/4-channel ? adc with easy drive input current cancellation and i 2 c interface typical application features applications description the ltc ? 2489 is a 4-channel (2-channel differential), 16-bit, no latency ? ? adc with easy drive technology and a 2-wire, i 2 c interface. the patented sampling scheme eliminates dynamic input current errors and the shortcom- ings of on-chip buffering through automatic cancellation of differential input current. this allows large external source impedances and rail-to-rail input signals to be directly digitized while maintaining exceptional dc accuracy. the ltc2489 includes an integrated oscillator. this device can be con? gured to measure an external signal from com- binations of 4 analog input channels operating in single- ended or differential modes. it automatically rejects line frequencies of 50hz and 60hz simultaneously. the ltc2489 allows a wide, common mode input range (0v to v cc ), independent of the reference voltage. any combination of single-ended or differential inputs can be selected and the ? rst conversion, after a new channel is selected, is valid. access to the multiplexer output enables optional external ampli? ers to be shared between all analog inputs and auto calibration continuously removes their associated offset and drift. data acquisition system with temperature compensation up to 2 differential or 4 single-ended inputs easy drive tm technology enables rail-to-rail inputs with zero differential input current directly digitizes high impedance sensors with full accuracy 2-wire i 2 c interface with 9 addresses plus one global address for synchronization 600nv rms noise (0.02lsb transition noise) gnd to v cc input/reference common mode range simultaneous 50hz/60hz rejection 2ppm inl, no missing codes 1ppm offset and 15ppm full-scale error no latency: digital filter settles in a single cycle, even after a new channel is selected single supply, 2.7v to 5.5v operation (0.8mw) internal oscillator tiny 4mm 3mm dfn package direct sensor digitizer direct temperature measurement instrumentation industrial process control +fs error vs r source at in + and in C sda scl f o ref + v cc 2.7v to 5.5v 0.1 f com ref 16-bit ? adc with easy-drive 4-channel mux in + in 2489 ta01a 2-wire i 2 c interface 1.7k ca1 ca0 9-pin selectable addresses ch0 ch1 ch3 ch2 10 f osc , lt, ltc and ltm are registered trademarks of linear technology corporation. no latency ? and easy drive are trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
ltc2489 2 2489f absolute maximum ratings (notes 1, 2) lead free finish tape and reel part marking package description temperature range ltc2489cde#pbf ltc2489ide#pbf ltc2489cde#trpbf ltc2489ide#trpbf 2489 2489 14-lead (4mm 3mm) plastic dfn 14-lead (4mm 3mm) plastic dfn 0c to 70c ?40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ 1 2 3 4 5 6 7 14 13 12 11 10 9 8 ref e ref + v cc ch3 ch2 ch1 ch0 f o ca0 ca1 scl sda gnd com de package 14-lead (4mm 3mm) plastic dfn 15 t jmax = 125c, e ja = 37c/w exposed pad (pin 15) is gnd, must be soldered to pcb order information supply voltage (v cc ) ................................... ?0.3v to 6v analog input voltage (ch0 to ch3, com) .................. ?0.3v to (v cc + 0.3v) ref + , ref ? .................................... ?0.3v to (v cc + 0.3v) digital input voltage ...................... ?0.3v to (v cc + 0.3v) digital output voltage ................... ?0.3v to (v cc + 0.3v) operating temperature range ltc2489c ................................................ 0c to 70c ltc2489i ............................................. ?40c to 85c storage temperature range ................... ?65c to 150c pin configuration
ltc2489 3 2489f electrical characteristics the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (notes 3, 4) parameter conditions min typ max units resolution (no missing codes) 0.1v v ref v cc , Cfs v in +fs (note 5) 16 bits integral nonlinearity 5v v cc 5.5v, v ref = 5v, v in(cm) = 2.5v (note 6) 2.7v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v (note 6) 2 1 20 ppm of v ref ppm of v ref offset error 2.5v v ref v cc , gnd in + = in C v cc (note 13) 0.5 2.5 v offset error drift 2.5v v ref v cc , gnd in + = in C v cc 10 nv/c positive full-scale error 2.5v v ref v cc , in + = 0.75v ref , in C = 0.25v ref 32 ppm of v ref positive full-scale error drift 2.5v v ref v cc , in + = 0.75v ref , in C = 0.25v ref 0.1 ppm of v ref /c negative full-scale error 2.5v v ref v cc , in + = 0.25v ref , in C = 0.75v ref 32 ppm of v ref negative full-scale error drift 2.5v v ref v cc , in + = 0.25v ref , in C = 0.75v ref 0.1 ppm of v ref /c total unadjusted error 5v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v 5v v cc 5.5v, v ref = 5v, v in(cm) = 2.5v 2.7v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v 15 15 15 ppm of v ref ppm of v ref ppm of v ref output noise 2.7v < v cc < 5.5v, 2.5v v ref v cc , gnd in + = in C v cc (note 12) 0.6 v rms converter characteristics the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) parameter conditions min typ max units input common mode rejection dc 2.5v v ref v cc , gnd in + = in C v cc (note 5) 140 db input normal mode rejection 50hz/60hz 2% 2.5v v ref v cc , gnd in + = in C v cc (notes 5, 9) 87 db reference common mode rejection dc 2.5v v ref v cc , gnd in + = in C v cc (note 5) 120 140 db power supply rejection dc v ref = 2.5v, in + = in C = gnd 120 db power supply rejection, 50hz 2% v ref = 2.5v, in + = in C = gnd (notes 7, 9) 120 db power supply rejection, 60hz 2% v ref = 2.5v, in + = in C = gnd (notes 8, 9) 120 db analog input and reference the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) symbol parameter conditions min typ max units in + absolute/common mode in + voltage (in + corresponds to the selected positive input channel) gnd C 0.3v v cc + 0.3v v in C absolute/common mode in C voltage (in C corresponds to the selected negative input channel) gnd C 0.3v v cc + 0.3v v v in input differential voltage range (in + C in C ) Cfs +fs v fs full scale of the differential input (in + C in C ) 0.5v ref v lsb least signi? cant bit of the output code fs/2 16 ref + absolute/common mode ref + voltage 0.1 v cc v ref C absolute/common mode ref C voltage gnd ref + C 0.1v v v ref reference voltage range (ref + C ref C ) 0.1 v cc v cs(in + )in + sampling capacitance 11 pf cs(in C )in C sampling capacitance 11 pf cs(v ref )v ref sampling capacitance 11 pf i dc_leak(in + ) in + dc leakage current sleep mode, in + = gnd C10 1 10 na
ltc2489 4 2489f i 2 c inputs and digital outputs the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) symbol parameter conditions min typ max units v ih high level input voltage 0.7v cc v v il low level input voltage 0.3v cc v v iha high level input voltage for address pins ca0, ca1 0.95v cc v v ila low level input voltage for address pins ca0, ca1 0.05v cc v r inh resistance from ca0, ca1 to v cc to set chip address bit to 1 10 k r inl resistance from ca0, ca1 to gnd to set chip address bit to 0 10 k r inf resistance from ca0, ca1 to gnd or v cc to set chip address bit to float 2 m i i digital input current C10 10 a v hys hysteresis of schmidt trigger inputs (note 5) 0.05v cc v v ol low level output voltage (sda) i = 3ma 0.4 v t of output fall time v ih(min) to v il(max) bus load c b 10pf to 400pf (note 14) 20 + 0.1c b 250 ns i in input leakage 0.1v cc v in v cc 1a c cax external capacitative load on chip address pins (ca0, ca1) for valid float 10 pf power requirements the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) symbol parameter conditions min typ max units v cc supply voltage 2.7 5.5 v i cc supply current conversion current (note 11) sleep mode (note 11) 160 1 275 2 a a analog input and reference the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) i dc_leak(in C ) in C dc leakage current sleep mode, in C = gnd C10 1 10 na i dc_leak(ref + ) ref + dc leakage current sleep mode, ref + = v cc C100 1 100 na i dc_leak(ref C ) ref C dc leakage current sleep mode, ref C = gnd C100 1 100 na t open mux break-before-make 50 ns qirr mux off isolation v in = 2v p-p dc to 1.8mhz 120 db
ltc2489 5 2489f symbol parameter conditions min typ max units f eosc external oscillator frequency range (note 16) 10 4000 khz t heo external oscillator high period 0.125 50 s t leo external oscillator low period 0.125 50 s t conv conversion time internal oscillator external oscillator (note 10) 144.1 146.9 41036/f eosc (in khz) 149.9 ms ms digital inputs and digital outputs the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) symbol parameter conditions min typ max units f scl scl clock frequency 0 400 khz t hd(sta) hold time (repeated) start condition 0.6 s t low low period of the scl pin 1.3 s t high high period of the scl pin 0.6 s t su(sta) set-up time for a repeated start condition 0.6 s t hd(dat) data hold time 00.9s t su(dat) data set-up time 100 ns t r rise time for sda signals (note 14) 20 + 0.1c b 300 ns t f fall time for sda signals (note 14) 20 + 0.1c b 300 ns t su(sto) set-up time for stop condition 0.6 s i 2 c timing characteristics the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3, 15) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd. note 3: v cc = 2.7v to 5.5v unless otherwise speci? ed. v refcm = v ref /2, f s = 0.5v ref v in = in + C in C , v in(cm) = (in + C in C )/2, where in + and in C are the selected input channels. note 4: use internal conversion clock or external conversion clock source with f eosc = 307.2khz unless otherwise speci? ed. note 5: guaranteed by design, not subject to test. note 6: integral nonlinearity is de? ned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: f eosc = 256khz 2% (external oscillator). note 8: f eosc = 307.2khz 2% (external oscillator). note 9: simultaneous 50hz/60hz (internal oscillator) or f eosc = 280khz 2% (external oscillator). note 10: the external oscillator is connected to the f o pin. the external oscillator frequency, f eosc , is expressed in khz. note 11: the converter uses its internal oscillator. note 12: the output noise includes the contribution of the internal calibration operations. note 13: guaranteed by design and test correlation. note 14: c b = capacitance of one bus line in pf (10pf c b 400pf). note 15: all values refer to v ih(min) and v il(max) levels. note 16: refer to applications information section for performance versus data rate graphs.
ltc2489 6 2489f input voltage (v) ? inl (ppm of v ref ) ? 1 3 ? 0 2 ?.5 ?.5 0.5 1.5 2489 g01 2.5 ? ?.5 ? 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v f o = gnd 85 c ?5 c 25 c input voltage (v) ? inl (ppm of v ref ) ? 1 3 ? 0 2 0.75 0.25 0.25 0.75 2489 g02 1.25 ?.25 v cc = 5v v ref = 2.5v v in(cm) = 1.25v f o = gnd ?5 c, 25 c, 85 c input voltage (v) ? inl (ppm of v ref ) ? 1 3 ? 0 2 0.75 0.25 0.25 0.75 2489 g03 1.25 ?.25 v cc = 2.7v v ref = 2.5v v in(cm) = 1.25v f o = gnd ?5 c, 25 c, 85 c input voltage (v) ?2 tue (ppm of v ref ) ? 4 12 ? 0 8 ?.5 ?.5 0.5 1.5 2489 g04 2.5 ? ?.5 ? 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v f o = gnd 85 c 25 c ?5 c input voltage (v) ?2 tue (ppm of v ref ) ? 4 12 ? 0 8 0.75 0.25 0.25 0.75 2489 g05 1.25 ?.25 v cc = 5v v ref = 2.5v v in(cm) = 1.25v f o = gnd 85 c 25 c ?5 c input voltage (v) ?2 tue (ppm of v ref ) ? 4 12 ? 0 8 0.75 0.25 0.25 0.75 2489 g06 1.25 ?.25 v cc = 2.7v v ref = 2.5v v in(cm) = 1.25v f o = gnd 85 c 25 c ?5 c typical performance characteristics integral nonlinearity (v cc = 5v, v ref = 5v) integral nonlinearity (v cc = 5v, v ref = 2.5v) integral nonlinearity (v cc = 2.7v, v ref = 2.5v) total unadjusted error (v cc = 5v, v ref = 5v) total unadjusted error (v cc = 5v, v ref = 2.5v) total unadjusted error (v cc = 2.7v, v ref = 2.5v) v in(cm) (v) ? offset error (ppm of v ref ) 0.1 0.2 0.3 24 2489 g07 0 0.1 01 356 0.2 0.3 v cc = 5v v ref = 5v v in = 0v t a = 25 c f o = gnd temperature ( c) ?5 0.3 offset error (ppm of v ref ) 0.2 0 0.1 0.2 ?5 15 30 90 2489 g08 0.1 ?0 0 45 60 75 0.3 v cc = 5v v ref = 5v v in = 0v f o = gnd v cc (v) 2.7 offset error (ppm of v ref ) 0.1 0.2 0.3 3.9 4.7 2489 g09 0 0.1 3.1 3.5 4.3 5.1 5.5 0.2 0.3 ref + = 2.5v ref = gnd v in = 0v v in(cm) = gnd t a = 25 c f o = gnd offset error vs v in(cm) offset error vs temperature offset error vs v cc
ltc2489 7 2489f v ref (v) 0 0.3 offset error (ppm of v ref ) 0.2 0.1 0 0.1 0.2 0.3 1234 2489 g10 5 v cc = 5v ref = gnd v in = 0v v in(cm) = gnd t a = 25 c f o = gnd temperature ( c) ?5 ?0 300 frequency (khz) 304 310 ?5 30 45 2489 g11 302 308 306 15 0 60 75 90 v cc = 4.1v v ref = 2.5v v in = 0v v in(cm) = gnd f o = gnd v cc (v) 2.7 300 frequency (khz) 302 304 306 308 310 3.0 3.5 4.0 4.5 2489 g12 5.0 5.5 v ref = 2.5v v in = 0v v in(cm) = gnd f o = gnd t a = 25 c typical performance characteristics offset error vs v ref on-chip oscillator frequency vs temperature on-chip oscillator frequency vs v cc frequency at v cc (hz) 1 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 1k 100k 2489 g13 10 100 10k 1m rejection (db) v cc = 4.1v dc 0.7v v ref = 2.5v in + = gnd in = gnd f o = gnd t a = 25 c frequency at v cc (hz) 0 ?40 rejection (db) ?20 ?0 ?0 ?0 0 20 100 140 2489 g14 ?00 ?0 80 180 220 200 40 60 120 160 v cc = 4.1v dc 1.4v v ref = 2.5v in + = gnd in = gnd f o = gnd t a = 25 c frequency at v cc (hz) 30600 ?0 ?0 0 30750 2489 g15 ?0 ?00 30650 30700 30800 ?20 ?40 ?0 rejection (db) v cc = 4.1v dc 0.7v v ref = 2.5v in + = gnd in = gnd f o = gnd t a = 25 c temperature ( c) ?5 100 conversion current ( a) 120 160 180 200 ?5 15 30 90 2489 g16 140 ?0 0 45 60 75 v cc = 5v v cc = 2.7v f o = gnd temperature ( c) ?5 0 sleep mode current ( a) 0.2 0.6 0.8 1.0 2.0 1.4 ?5 15 30 90 2489 g17 0.4 1.6 1.8 1.2 ?0 0 45 60 75 v cc = 5v v cc = 2.7v f o = gnd output data rate (readings/sec) 0 supply current ( a) 500 450 400 350 300 250 200 150 100 80 2489 g18 20 40 60 100 70 10 30 50 90 v cc = 5v v cc = 3v v ref = v cc in + = gnd in = gnd t a = 25 c psrr vs frequency at v cc psrr vs frequency at v cc psrr vs frequency at v cc conversion current vs temperature sleep mode current vs temperature conversion current vs output data rate
ltc2489 8 2489f f o (pin 1): frequency control pin. digital input that controls the internal conversion clock rate. when f o is connected to gnd, the converter uses its internal oscillator running at 307.2khz. the conversion clock may also be overridden by driving the f o pin with an external clock in order to change the output rate and the digital ? lter rejection null. ca0, ca1 (pins 2, 3): chip address control pins. these pins are con? gured as a three-state (low, high, floating) address control bits for the devices i 2 c address. scl (pin 4): serial clock pin of the i 2 c interface. the ltc2489 can only act as a slave and the scl pin only ac- cepts an external serial clock. data is shifted into the sda pin on the rising edges of the scl clock and output through the sda pin on the falling edges of the scl clock. sda (pin 5): bidirectional serial data line of the i 2 c interface. in the transmitter mode (read), the conver- sion result is output through the sda pin, while in the receiver mode (write), the device channel select bits are input through the sda pin. the pin is high impedance during the data input mode and is an open drain output (requires an appropriate pull-up device to v cc ) during the data output mode. gnd (pin 6): ground. connect this pin to a common ground plane through a low impedance connection. com (pin 7): the common negative input (in C ) for all single-ended multiplexer con? gurations. the voltage on ch0-ch3 and com pins can have any value between gnd C 0.3v to v cc + 0.3v. within these limits, the two selected inputs (in + and in C ) provide a bipolar input range (v in = in + C in C ) from C0.5 ? v ref to 0.5 ? v ref . outside this input range, the converter produces unique over-range and under-range output codes. ch0 to ch3 (pin 8-pin 11): analog inputs. may be pro- grammed for single-ended or differential mode. v cc (pin 12): positive supply voltage. bypass to gnd with a 10f tantalum capacitor in parallel with a 0.1f ceramic capacitor as close to the part as possible. ref + , ref C (pin 13, pin 14): differential reference input. the voltage on these pins can have any value between gnd and v cc as long as the reference positive input, ref + , remains more positive than the negative reference input, ref C , by at least 0.1v. the differential voltage (v ref = ref + C ref C ) sets the full-scale range for all input channels. exposed pad (pin 15): ground. this pin is ground and must be soldered to the pcb ground plane. for prototyping purposes, this pin may remain ? oating. pin functions functional block diagram autocalibration and control differential 3rd order ? modulator decimating fir address internal oscillator i 2 c interface gnd v cc ch0 ch1 ch2 ch3 com mux in + in ca0 scl ref + ref ca1 sda f o (int/ext) 2489 bd + 1.7k
ltc2489 9 2489f converter operation converter operation cycle the ltc2489 is a multichannel, low power, delta-sigma analog-to-digital converter with a 2-wire, i 2 c interface. its operation is made up of four states (see figure 1). the converter operating cycle begins with the conver- sion, followed by the sleep state and ends with the data input/output cycle . applications information figure 1. state transition table conversion sleep 2489 f01 yes no acknowledge yes no stop or read 24 bits data output/input power-on reset default input channel: in + = ch0, in = ch1 the ltc2489 is addressed for a read operation, the device begins outputting the conversion result under the control of the serial clock (scl). there is no latency in the conver- sion result. the data output is 24 bits long and contains a 16-bit plus sign conversion result. data is updated on the falling edges of scl allowing the user to reliably latch data on the rising edge of scl. a new conversion is initiated by a stop condition following a valid write operation or an incomplete read operation. the conversion automatically begins at the conclusion of a complete read cycle (all 24 bits read out of the device). ease of use the ltc2489 data output has no latency, ? lter settling delay, or redundant data associated with the conversion cycle. there is a one-to-one correspondence between the conversion and the output data. therefore, multiplexing multiple analog inputs is straightforward. each conversion, immediately following a newly selected input is valid and accurate to the full speci? cations of the device. the ltc2489 automatically performs offset and full-scale calibration every conversion cycle independent of the input channel selected. this calibration is transparent to the user and has no effect on the operation cycle de- scribed above. the advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage variation, input channel, and temperature drift. easy drive input current cancellation the ltc2489 combines a high precision, delta-sigma adc with an automatic, differential, input current cancellation front end. a proprietary front end passive sampling network transparently removes the differential input current. this enables external rc networks and high impedance sen- sors to directly interface to the ltc2489 without external ampli? ers. the remaining common mode input current is eliminated by either balancing the differential input im- pedances or setting the common mode input equal to the common mode reference (see the automatic differential input current cancellation section). this unique architec- ture does not require on-chip buffers, thereby enabling signals to swing beyond ground and v cc . moreover, the initially, at power-up, the ltc2489 performs a conver- sion. once the conversion is complete, the device enters the sleep state. in the sleep state, power consumption is reduced by two orders of magnitude. the part remains in the sleep state as long it is not addressed for a read/write operation. the conversion result is held inde? nitely in a static shift register while the part is in the sleep state. the device will not acknowledge an external request dur- ing the conversion state. after a conversion is ? nished, the device is ready to accept a read/write request. once
ltc2489 10 2489f cancellation does not interfere with the transparent offset and full-scale auto-calibration and the absolute accuracy (full scale + offset + linearity + drift) is maintained even with external rc networks. power-up sequence the ltc2489 automatically enters an internal reset state when the power supply voltage, v cc , drops below ap- proximately 2.0v. this feature guarantees the integrity of the conversion result and input channel selection. when v cc rises above this threshold, the converter creates an internal power-on-reset (por) signal with a duration of approximately 4ms. the por signal clears all internal registers. the conversion immediately following a por cycle is performed on the input channels in + = ch0 and in C = ch1. the ? rst conversion following a por cycle is accurate within the speci? cation of the device if the power supply voltage is restored to (2.7v to 5.5v) before the end of the por interval. a new input channel can be programmed into the device during this ? rst data input/ output cycle. reference voltage range this converter accepts a truly differential, external refer- ence voltage. the absolute/common mode voltage range for the ref + and ref C pins covers the entire operating range of the device (gnd to v cc ). for correct converter operation, v ref must be positive (ref + > ref C ). the ltc2489 differential reference input range is 0.1v to v cc . for the simplest operation, ref + can be shorted to v cc and ref C can be shorted to gnd. the converter output noise is determined by the thermal noise of the front end circuits. since the transition noise is well below 1lsb (0.02lsb), a decrease in reference voltage will proportionally improve the converter resolution and improve inl. input voltage range the analog inputs are truly differential with an absolute, common mode range for the ch0-ch3 and com input pins extending from gnd C 0.3v to v cc + 0.3v. within these limits, the ltc2489 converts the bipolar differen- tial input signal v in = in + C in C (where in + and in C are the selected input channels), from Cfs = C0.5 ? v ref to +fs = 0.5 ? v ref where v ref = ref + - ref C . outside this range, the converter indicates the overrange or the underrange condition using distinct output codes (see table 1). in order to limit any fault current due to input esd leakage current, resistors of up to 5k may be added in series with the input. the effect of series resistance on the converter accuracy can be evaluated from the curves presented in the input current/reference current sections. in addition, series resistors will introduce a temperature dependent error due to input leakage current. a 1na input leakage current will develop a 1ppm offset error on a 5k resistor if v ref = 5v. this error has a very strong temperature dependency. i 2 c interface the ltc2489 communicates through an i 2 c interface. the i 2 c interface is a 2-wire open-drain interface supporting multiple devices and multiple masters on a single bus. the connected devices can only pull the data line (sda) low and can never drive it high. sda is required to be externally connected to the supply through a pull-up resistor. when the data line is not being driven, it is high. data on the i 2 c bus can be transferred at rates up to 100kbits/s in the standard mode and up to 400kbits/s in the fast mode. each device on the i 2 c bus is recognized by a unique address stored in that device and can operate either as a transmitter or receiver, depending on the function of the device. in addition to transmitters and receivers, devices can also be considered as masters or slaves when perform- ing data transfers. a master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. devices addressed by the master are considered a slave. the ltc2489 can only be addressed as a slave. once ad- dressed, it can receive channel selection bits or transmit the last conversion result. the serial clock line, scl, is always an input to the ltc2489 and the serial data line sda is bidirectional. the device supports the standard mode and the fast mode for data transfer speeds up to 400kbits/s. figure 2 shows the de? nition of the i 2 c timing. applications information
ltc2489 11 2489f the start and stop conditions a start (s) condition is generated by transitioning sda from high to low while scl is high. the bus is considered to be busy after the start condition. when the data transfer is ? nished, a stop (p) condition is generated by transitioning sda from low to high while scl is high. the bus is free after a stop is generated. start and stop conditions are always generated by the master. when the bus is in use, it stays busy if a repeated start (sr) is generated instead of a stop condition. the repeated start timing is functionally identical to the start and is used for writing and reading from the device before the initiation of a new conversion. data transferring after the start condition, the i 2 c bus is busy and data transfer can begin between the master and the addressed slave. data is transferred over the bus in groups of nine bits, one byte followed by one acknowledge (ack) bit. the master releases the sda line during the ninth scl clock cycle. the slave device can issue an ack by pulling sda low or issue a not acknowledge (nak) by leaving the sda line high impedance (the external pull-up resistor will hold the line high). change of data only occurs while the clock line (scl) is low. data format after a start condition, the master sends a 7-bit address followed by a read/write (r/w) bit. the r/w bit is 1 for a read request and 0 for a write request. if the 7-bit ad- dress matches the hard wired, ltc2489s address (one of 9 pin-selectable addresses) the device is selected. when the device is addressed during the conversion state, it will not acknowledge r/w requests and will issue a nak by leaving the sda line high. if the conversion is complete, the ltc2489 issues an ack by pulling the sda line low. the ltc2489 has two registers. the output register (24 bits long) contains the last conversion result. the input register (8 bits long) sets the input channel. data output format the output register contains the last conversion result. after each conversion is completed, the device automati- cally enters the sleep state where the supply current is reduced to 1a. when the ltc2489 is addressed for a read operation, it acknowledges (by pulling sda low) and acts as a transmitter. the master/receiver can read up to three bytes from the ltc2489. after a complete read operation (3 bytes), a new conversion is initiated. the device will nak subsequent read operations while a conversion is being performed. the data output stream is 24 bits long and is shifted out on the falling edges of scl (see figure 3a). the ? rst bit is the conversion result sign bit (sig) (see tables 1 and 2). this bit is high if v in 0 and low if v in < 0 (where v in corresponds to the selected input signal in + C in C ). the second bit is the most signi? cant bit (msb) of the result. the ? rst two bits (sig and msb) can be used to indicate over and under range conditions (see table 2). if both bits are high, the differential input voltage is equal to or above +fs. if both bits are set low, the input voltage is below Cfs. the function of these bits is summarized in table 2. the 16 bits following the msb bit are the conversion sda scl ssrps t hd(sda) t hd(dat) t su(sta) t su(sto) t su(dat) t low t hd(sda) t sp t buf t r t f t r t f t high 2489 f02 figure 2. de? nition of timing for fast/standard mode devices on the i 2 c bus applications information
ltc2489 12 2489f result in binary twos complement format. the remaining six bits are always 0. as long as the voltage on the selected input channels (in + and in C ) remains between C0.3v and v cc + 0.3v (absolute maximum operating range) a conversion result is gener- ated for any differential input voltage v in from Cfs = C0.5 ? v ref to +fs = 0.5 ? v ref . for differential input voltages greater than +fs, the conversion result is clamped to the value corresponding to +fs. for differential input voltages below Cfs, the conversion result is clamped to the value Cfs C 1lsb. table 2. ltc2489 status bits input range bit 23 sig bit 22 msb v in fs 1 1 0v v in < fs 1 0 Cfs v in < 0v 0 1 v in < Cfs 0 0 input data format the ltc2489 serial input is 8 bits long and is written into the device in one 8-bit word. sgl, odd, a2, a1, a0 are used to select the input channel. after power-up, the device initiates an internal reset cycle which sets the input channel to ch0-ch1 (in + = ch0, in C = ch1). the ? rst conversion automatically begins at power-up using this default input channel. once the table 1. output data format differential input voltage v in * bit 23 sig bit 22 msb bit 21 bit 20 bit 19 bit 6 lsb bits 5-0 always 0 v in * fs** 1 1 0 0 0 0 000000 fs** C 1lsb 1 0 1 1 1 1 000000 0.5 ? fs** 1 0 1 0 0 0 000000 0.5 ? fs** C 1lsb 1 0 0 1 1 1 000000 0 1 0 0 0 0 0 000000 C1lsb 0 1 1 1 1 1 000000 C0.5 ? fs** 0 1 1 0 0 0 000000 C0.5 ? fs** C 1lsb 0 1 0 1 1 1 000000 Cfs** 0 1 0 0 0 0 000000 v in * < Cfs** 0 0 1 1 1 1 000000 *the differential input voltage v in = in + C in C . **the full-scale voltage fs = 0.5 ? v ref . conversion is complete, a new channel may be written into the device. the ? rst three bits of the input word consist of two pre- amble bits and one enable bit. these three bits are used to enable the input channel selection. valid settings for these three bits are 000, 100, and 101. other combinations should be avoided. if the ? rst three bits are 000 or 100, the following data is ignored (dont care) and the previously selected input channel remains valid for the next conversion. if the ? rst three bits shifted into the device are 101, then the next ? ve bits select the input channel for the next conversion cycle (see table 3). applications information table 3 channel selection mux address channel selection sgl odd/ sign a2 a1 a0 0 1 2 3 com *00000in + in C 00001 in + in C 01000in C in + 01001 in C in + 10000in + in C 10001 in + in C 11000 in + in C 11001 in + in C *default at power up
ltc2489 13 2489f figure 3a. timing diagram for reading from the ltc2489 sleep data output ack by ltc2489 ack by master always low start by master nak by master lsb r msb sig d23 7 89 1 2 9 1 2 3 4 5 6 7 8 9 1 7-bit address 2489 f03a scl sda ack by ltc2489 ack by ltc2489 nak by ltc2489 start by master sgl odd w 0 1 scl sda en a2 a1 a0 7 ?9 2 1 2 3 4 5 6 7 8 9 1 7-bit address 2489 f03b xx xxx xxx sleep data input 19 234 56 78 figure 3b. timing diagram for writing to the ltc2489 the ? rst input bit (sgl) following the 101 sequence de- termines if the input selection is differential (sgl = 0) or single-ended (sgl = 1). for sgl = 0, two adjacent chan- nels can be selected to form a differential input. for sgl = 1, one of 4 channels is selected as the positive input. the negative input is com for all single-ended operations. the remaining four bits (odd, a2, a1, a0) determine which channel(s) is/are selected and the polarity (for a differential input). initiating a new conversion when the ltc2489 ? nishes a conversion, it automatically enters the sleep state. once in the sleep state, the device is ready for a read operation. after the device acknowledges a read request, the device exits the sleep state and enters the data output state. the data output state concludes and the ltc2489 starts a new conversion once a stop condition is issued by the master or all 24 bits of data are read out of the device. during the data read cycle, a stop command may be issued by the master controller in order to start a new conversion and abort the data transfer. this stop command must be issued during the ninth clock cycle of a byte read when the bus is free (the ack/nak cycle). ltc2489 address the ltc2489 has two address pins (ca0, ca1). each may be tied high, low, or left ? oating enabling one of 9 possible addresses (see table 4). in addition to the con? gurable addresses listed in table 4, the ltc2489 also contains a global address (1110111) which may be used for synchronizing multiple ltc2489s or other ltc24xx delta-sigma i 2 c devices, (see syn- chronizing multiple ltc2489s with global address call section). applications information
ltc2489 14 2489f operation sequence the ltc2489 acts as a transmitter or receiver, as shown in figure 4. the device may be programmed to select an input channel, differential or single-ended mode, and channel polarity. table 4. address assignment ca1 ca0 address low low 0010100 low high 0010110 low float 0010101 high low 0100110 high high 0110100 high float 0100111 float low 0010111 float high 0100101 float float 0100100 continuous read in applications where the input channel does not need to change for each cycle, the conversion can be continuously performed and read without a write cycle (see figure 5). the input channel remains unchanged from the last value written into the device. if the device has not been written to since power up, the channel selection is set to the default value of ch0 = in + , ch1 = in C . at the end of a read operation, a new conversion automatically begins. at the conclusion of the conversion cycle, the next result may be read using the method described above. if the conversion cycle is not concluded and a valid address selects the device, the ltc2489 generates a nak signal indicating the conversion cycle is in progress. continuous read/write once the conversion cycle is concluded, the ltc2489 can be written to and then read from using the repeated start (sr) command. applications information s ack data sr data transferring p 7-bit address r/w 2489 f04 conversion conversion sleep data input/output 7-bit address 7-bit address ss rr ack ack read read pp 2489 f05 conversion conversion conversion sleep data output data input sleep figure 4. conversion sequence figure 5. consecutive reading with the same input/con? guration
ltc2489 15 2489f 7-bit address 7-bit address s r w ack ack write sr p read 2489 f06 conversion conversion address sleep data output data input 7-bit address s w ack write (optional) p 2489 f07 conversion conversion sleep data input figure 6. write, read, start conversion figure 7. start a new conversion without reading old conversion result applications information figure 6 shows a cycle which begins with a data write, a repeated start, followed by a read and concluded with a stop command. the following conversion begins after all 24 bits are read out of the device or after a stop com- mand. the following conversion will be performed using the newly programmed data. discarding a conversion result and initiating a new conversion with optional write at the conclusion of a conversion cycle, a write cycle can be initiated. once the write cycle is acknowledged, a stop command will start a new conversion. if a new input channel is required, this data can be written into the device and a stop command will initiate the next conversion (see figure 7). synchronizing multiple ltc2489s with a global address call in applications where several ltc2489s (or other i 2 c delta-sigma adcs from linear technology corporation) are used on the same i 2 c bus, all converters can be syn- chronized through the use of a global address call. prior to issuing the global address call, all converters must have completed a conversion cycle. the master then issues a start, followed by the global address 1110111, and a write request. all converters will be selected and acknowledge the request. the master then sends a write byte (optional) followed by the stop command. this will update the chan- nel selection (optional) and simultaneously initiate a start of conversion for all delta-sigma adcs on the bus (see figure 8). in order to synchronize multiple converters global address scl sda s w ack write (optional) p 2489 f08 ltc2489 ltc2489 ltc2489 all ltc2489s in sleep conversion of all ltc2489s data input figure 8. synchronize multiple ltc2489s with a global address call
ltc2489 16 2489f without changing the channel, a stop may be issued after acknowledgement of the global write command. global read commands are not allowed and the converters will nak a global read request. driving the input and reference the input and reference pins of the ltc2489 are connected directly to a switched capacitor network. depending on the relationship between the differential input voltage and the differential reference voltage, these capacitors are switched between these four pins. each time a capacitor is switched between two of these pins, a small amount of charge is transferred. a simpli? ed equivalent circuit is shown in figure 9. when using the ltc2489s internal oscillator, the input capacitor array is switched at 123khz. the effect of the charge transfer depends on the circuitry driving the in- put/reference pins. if the total external rc time constant is less than 580ns the errors introduced by the sampling process are negligible since complete settling occurs. typically, the reference inputs are driven from a low impedance source. in this case, complete settling occurs even with large external bypass capacitors. the inputs (ch0-ch3, com), on the other hand, are typically driven from larger source resistances. source resistances up to 10k may interface directly to the ltc2489 and settle completely; however, the addition of external capacitors at the input terminals in order to ? lter unwanted noise (antialiasing) results in incomplete settling. automatic differential input current cancellation in applications where the sensor output impedance is low (up to 10k with no external bypass capacitor or up to 500 with 0.001f bypass), complete settling of the input occurs. in this case, no errors are introduced and direct digitization is possible. for many applications, the sensor output impedance combined with external input bypass capacitors produces rc time constants much greater than the 580ns required for 1ppm accuracy. for example, a 10k bridge driving a 0.1f capacitor has a time constant an order of magnitude greater than the required maximum. the ltc2489 uses a proprietary switching algorithm that forces the average differential input current to zero independent of external settling errors. this allows direct digitization of high impedance sensors without the need for buffers. the switching algorithm forces the average input current on the positive input (i in + ) to be equal to the average input current on the negative input (i in C ). over the complete conversion cycle, the average differential input current (i in + C i in C ) is zero. while the differential input current is applications information in + in 10k internal switch network 10k c eq 12 f 10k i in ref + i ref + i in + i ref 2489 f09 switching frequency f sw = 123khz internal oscillator f sw = 0.4 ?f eosc external oscillator ref 10k 100 input multiplexer 100 figure 9. equivalent analog input circuit iin iin vv r avg avg in cm ref cm eq + () = () = ? ? () () . 05 i iref vv v r avg ref ref cm in cm + () + () 15 05 . . () () e eq in ref eq ref ref cm v vr where v ref ref v : ( 2 =? +? ) ) , = ? ? ? ? ? ? ? ? =? +? +? + ref ref v in in where in an in 2 d d in are the selected input channels v in in cm ? + = () ?n ? ? ? ? ? ? ? ? ? = 2 r 2.98m internal oscillator r eq e eq 12 eosc 0.833 10 /f external oscillator =? ()
ltc2489 17 2489f zero, the common mode input current (i in + + i in C )/2 is proportional to the difference between the common mode input voltage (v in(cm) ) and the common mode reference voltage (v ref(cm) ). in applications where the input common mode voltage is equal to the reference common mode voltage, as in the case of a balanced bridge, both the differential and com- mon mode input current are zero. the accuracy of the converter is not compromised by settling errors. in applications where the input common mode voltage is constant but different from the reference common mode voltage, the differential input current remains zero while the common mode input current is proportional to the difference between v in(cm) and v ref(cm) . for a reference common mode voltage of 2.5v and an input common mode of 1.5v, the common mode input current is ap- proximately 0.74a. this common mode input current does not degrade the accuracy if the source impedances tied to in + and in C are matched. mismatches in source impedance lead to a ? xed offset error but do not effect the linearity or full-scale reading. a 1% mismatch in a 1k source resistance leads to a 74v shift in offset voltage. in applications where the common mode input voltage varies as a function of the input signal level (single-ended type sensors), the common mode input current varies proportionally with input voltage. for the case of balanced input impedances, the common mode input current effects are rejected by the large cmrr of the ltc2489, leading to little degradation in accuracy. mismatches in source impedances lead to gain errors proportional to the dif- ference between the common mode input and common mode reference. 1% mismatches in 1k source resistances lead to gain errors on the order of 15ppm. based on the stability of the internal sampling capacitors and the ac- curacy of the internal oscillator, a one-time calibration will remove this error. in addition to the input sampling current, the input esd protection diodes have a temperature dependent leakage current. this current, nominally 1na (10na max), results in a small offset shift. a 1k source resistance will create a 1v typical and a 10v maximum offset voltage. reference current similar to the analog inputs, the ltc2489 samples the differential reference pins (ref + and ref C ) transferring small amounts of charge to and from these pins, thus producing a dynamic reference current. if incomplete set- tling occurs (as a function the reference source resistance and reference bypass capacitance) linearity and gain errors are introduced. for relatively small values of external reference capacitance (c ref < 1nf), the voltage on the sampling capacitor settles for reference impedances of many k (if c ref = 100pf up to 10k will not degrade the performance) (see figures 10 and 11). applications information figure 10. +fs error vs r source at v ref (small c ref ) figure 11. Cfs error vs r source at v ref (small c ref ) r source ( ) 0 +fs error (ppm) 50 70 90 10k 2489 f10 30 10 40 60 80 20 0 ?0 10 100 1k 100k v cc = 5v v ref = 5v v in + = 3.75v v in = 1.25v f o = gnd t a = 25 c c ref = 0.01 f c ref = 0.001 f c ref = 100pf c ref = 0pf r source ( ) 0 ?s error (ppm) ?0 ?0 10 10k 2489 f11 ?0 ?0 ?0 ?0 0 ?0 ?0 ?0 10 100 1k 100k v cc = 5v v ref = 5v v in + = 1.25v v in = 3.75v f o = gnd t a = 25 c c ref = 0.01 f c ref = 0.001 f c ref = 100pf c ref = 0pf
ltc2489 18 2489f in cases where large bypass capacitors are required on the reference inputs (c ref > .01f), full-scale and linear- ity errors are proportional to the value of the reference resistance. every ohm of reference resistance produces a full-scale error of approximately 0.5ppm (while operat- ing with the internal oscillator) (see figures 12 and 13). if the input common mode voltage is equal to the reference common mode voltage, a linearity error of approximately 0.67ppm per 100 of reference resistance results (see figure 14). in applications where the input and reference common mode voltages are different, the errors increase. a 1v difference in between common mode input and common mode reference results in a 6.7ppm inl error for every 100 of reference resistance. in addition to the reference sampling charge, the reference esd protection diodes have a temperature dependent leak- age current. this leakage current, nominally 1na (10na max) results in a small, gain error. a 100 reference resistance will create a 0.5v full-scale error. normal mode rejection and antialiasing one of the advantages delta-sigma adcs offer over conventional adcs is on-chip digital ? ltering. combined with a large oversample ratio, the ltc2489 signi? cantly simpli? es antialiasing ? lter requirements. additionally, the input current cancellation feature allows external low pass ? ltering without degrading the dc performance of the device. applications information figure 14. inl vs differential input voltage and reference source resistance for c ref > 1f v in /v ref 0.5 inl (ppm of v ref ) 2 6 10 0.3 2489 f14 ? ? 0 4 8 ? ? ?0 0.3 0.1 0.1 0.5 v cc = 5v v ref = 5v v in(cm) = 2.5v t a = 25 c c ref = 10 f r = 1k r = 100 r = 500 figure 12. +fs error vs r source at v ref (large c ref ) figure 13. Cfs error vs r source at v ref (large c ref ) r source ( ) 0 +fs error (ppm) 300 400 500 800 2489 f12 200 100 0 200 400 600 1000 v cc = 5v v ref = 5v v in + = 3.75v v in = 1.25v f o = gnd t a = 25 c c ref = 1 f, 10 f c ref = 0.1 f c ref = 0.01 f r source ( ) 0 ?s error (ppm) ?00 ?00 0 800 2489 f13 ?00 ?00 ?00 200 400 600 1000 v cc = 5v v ref = 5v v in + = 1.25v v in = 3.75v f o = gnd t a = 25 c c ref = 1 f, 10 f c ref = 0.1 f c ref = 0.01 f
ltc2489 19 2489f the sinc 4 digital ? lter provides excellent normal mode rejection at all frequencies except dc and integer multiples of the modulator sampling frequency (f s ). the modulator sampling frequency is f s = 15,360hz while operating with its internal oscillator and f s = f eosc /20 when operating with an external oscillator of frequency f eosc . when using the internal oscillator, the ltc2489 is designed to reject line frequencies. as shown in figure 15, rejection nulls occur at multiples of frequency f n , where f n = 55hz for simultaneous 50hz/60hz rejection. multiples of the modulator sampling rate (f s = f n ? 256) only reject noise to 15db (see figure 16); if noise sources are present at these frequencies antialiasing will reduce their effects. the user can expect to achieve this level of performance using the internal oscillator, as shown in figure 17. measured values of normal mode rejection are shown superimposed over the theoretical values. traditional high order delta-sigma modulators suffer from potential instabilities at large input signal levels. the proprietary architecture used for the ltc2489 third order modulator resolves this problem and guarantees stability with input signals 150% of full scale. in many industrial applications, it is not uncommon to have microvolt level signals superimposed over unwanted error sources with several volts if peak-to-peak noise. figure 18 shows mea- surement results for the rejection of a 7.5v peak-to-peak noise source (150% of full scale) applied to the ltc2489. this curve shows that the rejection performance is main- tained even in extremely noisy environments. output data rate when using its internal oscillator, the ltc2489 produces up to 7.5 samples per second (sps) with a notch frequency of 60hz. the actual output data rate depends upon the length of the sleep and data output cycles which are controlled applications information input signal frequency (hz) input normal mode rejection (db) 2489 f15 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 f n 0 2f n 3f n 4f n 5f n 6f n 7f n 8f n f n = f eosc/5120 input signal frequency (hz) 250f n 252f n 254f n 256f n 258f n 260f n 262f n input normal mode rejection (db) 2489 f16 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 100 110 120 f n = f eosc/5120 figure 16. input normal mode rejection at f s = 256 ? f n figure 15. input normal mode rejection at dc
ltc2489 20 2489f by the user and can be made insigni? cantly short. when operating with an external conversion clock (f o connected to an external oscillator), the ltc2489 output data rate can be increased. the duration of the conversion cycle is 41036/f eosc . if f eosc = 307.2khz, the converter behaves as if the internal oscillator is used. an increase in f eosc over the nominal 307.2khz will trans- late into a proportional increase in the maximum output data rate (up to a maximum of 100sps). the increase in output rate leads to degradation in offset, full-scale error, and effective resolution as well as a shift in frequency rejection. a change in f eosc results in a proportional change in the internal notch position. this leads to reduced differential mode rejection of line frequencies. the common mode applications information rejection of line frequencies remains unchanged, thus fully differential input signals with a high degree of symmetry on both the in + and in C pins will continue to reject line frequency noise. an increase in f eosc also increases the effective dynamic input and reference current. external rc networks will continue to have zero differential input current, but the time required for complete settling (580ns for f eosc = 307.2khz) is reduced, proportionally. once the external oscillator frequency is increased above 1mhz (a more than 3x increase in output rate) the effective- ness of internal auto calibration circuits begins to degrade. this results in larger offset errors, full-scale errors, and decreased resolution, as shown in figures 19 to 26. input frequency (hz) 0 12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200 normal mode rejection (db) 2489 f17 0 ?0 ?0 ?0 ?0 100 120 v cc = 5v v ref = 5v v in(cm) = 2.5v v in(p-p) = 5v t a = 25 c measured data calculated data input frequency (hz) 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 normal mode rejection (db) 2489 f18 0 ?0 ?0 ?0 ?0 100 120 v cc = 5v v ref = 5v v in(cm) = 2.5v t a = 25 c v in(p-p) = 5v v in(p-p) = 7.5v (150% of full scale) figure 17. input normal mode rejection vs input frequency with input perturbation of 100% (50hz/60hz notch) figure 18. measure input normal mode rejection vs input frequency with input perturbation of 150% (60hz notch)
ltc2489 21 2489f output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 10 50 70 14 40 90 100 20 30 60 80 t a = 85 c t a = 25 c v in(cm) = v ref(cm) v cc = v ref = 5v f o = ext clock res = log 2 (v ref /inl max ) 2489 f23 output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 10 50 70 14 40 90 100 20 30 60 80 v cc = 5v, v ref = 2.5v v cc = v ref = 5v v in(cm) = v ref(cm) v in = 0v ref = gnd f o = ext clock t a = 25 c res = log 2 (v ref /inl max ) 2489 f26 figure 19. offset error vs output data rate and temperature figure 20. +fs error vs output data rate and temperature figure 21.Cfs error vs output data rate and temperature figure 22. resolution (noise rms 1lsb) vs output data rate and temperature figure 23. resolution (inl max 1lsb) vs output data rate and temperature figure 25. resolution (noise rms 1lsb) vs output data rate and temperature figure 26. resolution (inl max 1lsb) vs output data rate and temperature figure 24. offset error vs output data rate and temperature applications information output data rate (readings/sec) ?0 offset error (ppm of v ref ) 10 30 50 0 20 40 20 40 60 80 2489 f19 100 10 030507090 v in(cm) = v ref(cm) v cc = v ref = 5v v in = 0v f o = ext clock t a = 85 c t a = 25 c output data rate (readings/sec) 0 0 +fs error (ppm of v ref ) 500 1500 2000 2500 3500 10 50 70 2489 f20 1000 3000 40 90 100 20 30 60 80 v in(cm) = v ref(cm) v cc = v ref = 5v f o = ext clock t a = 85 c t a = 25 c output data rate (readings/sec) 0 ?500 ?s error (ppm of v ref ) ?000 ?000 ?500 ?000 0 10 50 70 2489 f21 ?500 ?00 40 90 100 20 30 60 80 v in(cm) = v ref(cm) v cc = v ref = 5v f o = ext clock t a = 85 c t a = 25 c output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 10 50 70 2489 f22 14 40 90 100 20 30 60 80 v in(cm) = v ref(cm) v cc = v ref = 5v v in = 0v f o = ext clock res = log 2 (v ref /noise rms ) t a = 25 c, 85 c output data rate (readings/sec) 0 ?0 offset error (ppm of v ref ) ? 5 10 20 10 50 70 2489 f24 0 15 40 90 100 20 30 60 80 v cc = 5v, v ref = 2.5v v cc = v ref = 5v v in(cm) = v ref(cm) v in = 0v f o = ext clock t a = 25 c output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 10 50 70 2489 f25 14 40 90 100 20 30 60 80 v in(cm) = v ref(cm) v in = 0v f o = ext clock t a = 25 c res = log 2 (v ref /noise rms ) v cc = 5v, v ref = 2.5v, 5v
ltc2489 22 2489f easy drive adcs simplify measurement of high impedance sensors delta-sigma adcs, with their high accuracy and high noise immunity, are ideal for directly measuring many types of sensors. nevertheless, input sampling currents can overwhelm high source impedances or low-bandwidth, micropower signal conditioning circuits. the ltc2489 solves this problem by balancing the input currents, thus simplifying or eliminating the need for signal conditioning circuits. a common application for a delta-sigma adc is thermistor measurement. figure 27 shows two examples of thermistor digitization bene? ting from the easy drive technology. the ? rst circuit (applied to input channels ch0 and ch1) uses balanced reference resistors in order to balance the common mode input/reference voltage and balance the differential input source resistance. if reference resistors r1 and r4 are exactly equal, the input current is zero and no errors result. if these resistors have a 1% tolerance, the maximum error in measured resistance is 1.6 due to a shift in common mode voltage; far less than the 1% error of the reference resistors themselves. no ampli? er is required, making this an ideal solution in micropower applications. easy drive also enables very low power, low bandwidth ampli? ers to drive the input to the ltc2489. as shown in figure 27, ch2 is driven by the lt1494. the lt1494 has excellent dc specs for an ampli? er with 1.5a supply current (the maximum offset voltage is 150v and the open loop gain is 100,000). its 2khz bandwidth makes it unsuitable for driving conventional delta sigma adcs. adding a 1k , 0.1f ? lter solves this problem by providing a charge reservoir that supplies the ltc2489 instantaneous current, while the 1k resistor isolates the capacitive load from the lt1494. conventional delta sigma adcs input sampling current lead to dc errors as a result of incomplete settling in the external rc network. the easy drive technology cancels the differential input current. by balancing the negative input (ch3) with a 1k , 0.1f network errors due to the common mode input current are cancelled. applications information
ltc2489 23 2489f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. de package 14-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1708 rev b) package description 3.00 0.10 (2 sides) 4.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wged-3) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?xposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 3.00 ref 1.70 0.05 1 7 14 8 pin 1 top mark (see note 6) 0.200 ref 0.00 ?0.05 (de14) dfn 0806 rev b pin 1 notch r = 0.20 or 0.35 45 chamfer 3.00 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 package outline 0.25 0.05 0.25 0.05 0.50 bsc 3.30 0.05 3.30 0.10 0.50 bsc
ltc2489 24 2489f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2007 lt 0307 ? printed in usa related parts typical application part number description comments lt1236a-5 precision bandgap reference, 5v 0.05% max initial accuracy, 5ppm/c drift lt1460 micropower series reference 0.075% max initial accuracy, 10ppm/c max drift lt1790 micropower sot-23 low dropout reference family 0.05% max initial accuracy, 10ppm/c max drift ltc2400 24-bit, no latency ? adc in so-8 0.3ppm noise, 4ppm inl, 10ppm total unadjusted error, 200a ltc2410 24-bit, no latency ? adc with differential inputs 0.8v rms noise, 2ppm inl ltc2440 high speed, low noise 24-bit ? adc 3.5khz output rate, 200nv noise, 24.6 enobs ltc2442 24-bit, high speed, 4-channel/2-channel ? adc with integrated ampli? er 8khz output rate, 220nv noise, simultaneous 50hz/60hz rejection ltc2449 24-bit, high speed, 8-channel/16-channel ? adc 8khz output rate, 200nv noise, simultaneous 50hz/60hz rejection ltc2480/ltc2482/ ltc2484 16-/24-bit ? adcs with easy drive inputs, 600nv noise, programmable gain, and temperature sensor pin compatible 16-bit and 24-bit versions ltc2481/ltc2483/ ltc2485 16-/24-bit ? adcs with easy drive inputs, 600nv noise, i 2 c interface, programmable gain, and temperature sensor pin compatible 16-bit and 24-bit versions ltc2486/ltc2488/ ltc2492 16-bit/24-bit 2-/4-channel ? adc with easy drive inputs, spi interface, programmable gain, and temperature sensor pin-compatible 16-bit and 24-bit versions ltc2487 16-bit 2-/4-channel ? adc with easy drive inputs and i 2 c interface pin-compatible ltc2493/ltc2489 ltc2493 24-bit 2-/4-channel ? adc with easy drive inputs, i 2 c interface and temperature sensor pin compatible ltc2487/ltc2489 ltc2495/ltc2497/ ltc2499 16-bit/24-bit 8-/16-channel ? adc with easy drive inputs and i 2 c interface, programmable gain, and temperature sensor pin-compatible 16-bit and 24-bit versions ltc2496/ltc2498 16-bit 8-/16-channel ? adc with easy drive inputs and spi interface pin-compatible with ltc2449/ltc2494 figure 27. easy drive adcs simplify measurement of high impedance sensors v cc f o scl sda gnd = external oscillator = internal oscillator ltc2489 2-wire i 2 c interface 9-pin selectable addresses 2489 f38 ca0 12 1 ref + 13 ref 14 ch0 8 ch1 9 ch2 10 ch3 11 com 7 4 2 6 3 5 5v 0.1 f 10 f ca1 i in + = 0 i in = 0 c4 0.1 f c3 0.1 f + 102k 5v 5v lt1494 0.1 f 0.1 f 0.1 f 1k 1k 10k to 100k 1.7k 5v r1 51.1k r4 51.1k r3 10k to 100k

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